The standard manufacture of spacers using dry etching is a technique that is widely used in microelectronics. This technique allows reproducible results to be achieved, and combines the ability to achieve relatively straight etching profiles with the achievement, in general, of good etching “selectivities”, that is, the ability to stop on another material without excessive consumption of the latter. On the other hand, it does not allow large volume spacers to be obtained, nor does it allow the width of said spacers to be controlled. The document “Highly Reliable Flash Memory with Self-aligned Split-gate Cells Embedded into High Performance 65 nm CMOS for Automotive and Smartcard Applications” ((IMW2012) by D. Shum et al.) states that the spacer profile obtained by using conventional microelectronics methods is substantially triangular. A spacer with such a triangular profile has two main drawbacks:                The thickness of the spacer is insufficient at the edge of the triangular patterns, and doping of the drain is therefore not very well controlled. Ideally, a square spacer would be required that is sufficiently thick to avoid potential counter-doping.        The width and the silicidation volume at the top of the spacer are small and making of contacts is difficult to accomplish.        
Such a structure is illustrated in FIG. 1, which schematically shows a dual gate memory cell 1 with a split-gate architecture wherein the storage transistor gate is made in the form of a spacer of the control transistor gate.
The memory 1 comprises a substrate 2 made from a semi-conductor material, a control transistor gate conductive area 3 which has a lateral flank 4 and a lateral spacer 5 arranged against the lateral flank 4 of the control transistor 3. This lateral spacer 5 in particular comprises:                a three-layer dielectric stack 6, for example of oxide-nitride-oxide (called an ONO stack), where the nitride layer stores electric charges;        a conductive area of the storage transistor gate 7 with a substantially triangular shape.        
With such a structure, however, it is very difficult to subsequently make a point of electrical contact on the conductive area of the storage transistor 7: the accessible area for making a contact is very small. Moreover, at the edge of the spacer the thickness of the conductive area of the storage transistor gate 7 is very small and poorly controlled; the drain doping area itself will therefore be poorly controlled.
Document US20110070726A1 proposes a method of manufacturing a spacer whose shape is not triangular. According to this manufacturing method, a protective material is deposited on the material of the spacer prior to the etching of the spacer. The protective material can contain carbon; it may also be a dielectric with, for example, an oxide or nitride base, such as silicon nitride. The protective material may be highly selective relative to the spacer material. This protective material contributes to the achievement of a spacer which has a non-triangular form and whose lateral flanks are substantially vertical. The manufacturing method proposed by document US20110070726A1 requires a chain of supplementary technological steps, however, which makes it more complex and costly.